The closest i ever got (for the CRS317 line) was this russian table:
that puts the 32port version of the 8xxx chipset at 4MB/ASIC, translating to probably 2MB on the CRS317 (16-port 8000 series Marvell SoC)
in the before times, the drivers used HoL buffering, which killed the whole switch whenever there was a speed mismatch between ports
somewhere (certainly on 6.49.x and 7.x.x) they fixed this (now it's FIFO, "drop-on-busy"), so that only the "low speed" ports get crappy performance
say i have a ring topology of 6*CRS317, with 30GB pipes between those, and 20GB active troughput
in one of the switches, there is a local feed of 1GB to Joe-Customer
that one port will drop packets like there's no tomorrow in the "downlink" direction (TX-Drop counter will increase, TCP will misbehave)
but the rest of the topology will remain unaffected.
Moral of the stoty:
So long as there are no speed mismatches, CRS will work beautifully
If there are speed mismatches (somehow using LACP makes it less bad), performance will be degraded, but only on the lowest-speed interface, in the "down" direction.
(some of this was discussed in this topic: viewtopic.php?t=185231
These Marvell chips are great, cheap, and power-efficient.
The way they do that is by not having giant on-die buffers. It's best to understand that, and work around this constraint, avoiding mismatches if at all possible.